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ITM 201

Microprocessor and Computer Architecture

TU BITM · Semester 3 · BITM curriculum and programme regulation

Requirement
required
Credits
3
Study Guide
8 units available

Chapter notes

Authoritative study guide across 8 syllabus units

Open a unit to read its study notes.

Unit 1: Introduction to Microprocessor· 6 LHs· ~8 marks

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Part 1: Core Concepts (2 Marks)

  • Microprocessor: A programmable, clock-driven, register-based semiconductor central processing unit (CPU) fabricated on a single integrated circuit (IC) that fetches, decodes, and executes binary instructions.
  • System Bus Triad:
    • Address Bus: Unidirectional; carries memory addresses (e.g. 16 bits in 8085 = 216=64 KB2^{16} = 64\text{ KB} address space).
    • Data Bus: Bidirectional; carries data words (8 bits in 8085).
    • Control Bus: Carries synchronization and timing signals (RD, WR, IO/M).
  • Simple-As-Possible (SAP-1) Computer: A basic 8-bit computer architecture designed by Malvino featuring a Program Counter (PC), Memory Address Register (MAR), 16x8 RAM, Instruction Register (IR), Controller/Sequencer, Accumulator (A), Adder/Subtractor, B Register, and Output Register.

Part 2: Structural Frameworks (10 Marks)

SAP-1 Architecture Block Diagram

W-Bus (8-bit Data Bus)

PC MAR 16x8 IR Accum Output
(4-bit (4-bit) RAM (8-bit A(8-b) Reg
Instruction Adder / Binary
Decoder Sub (8b) Display

Part 3: Distinction Tables

Basis of Comparison Von Neumann Architecture Harvard Architecture
Memory Structure Unified single memory for both program instructions and data. Physically separate memories and buses for instructions and data.
Bus Bottleneck Von Neumann bottleneck: cannot access data and code simultaneously. Simultaneous instruction fetch and data operand read/write.
Hardware Complexity Simpler hardware design; fewer bus traces. More complex motherboard and silicon pin routing.
Application General purpose CPUs (x86 desktop systems). Embedded DSPs, microcontrollers (ARM, PIC).

Part 4: Worked Problems & Exam Traps

Microprocessor Bus Address Space Calculation

Problem: Calculate the addressable memory capacity of a processor having a 24-bit address bus and an 8-bit data bus. Solution:

  1. Addressable locations: 224=24×220=16×1 MB=16 Mega-locations2^{24} = 2^4 \times 2^{20} = 16 \times 1\text{ MB} = 16\text{ Mega-locations}.
  2. Data word size: 8 bits=1 Byte8\text{ bits} = 1\text{ Byte}.
  3. Total memory capacity =16 MB×1 Byte=16 Megabytes (MB)= 16\text{ MB} \times 1\text{ Byte} = 16\text{ Megabytes (MB)}.

Address bus determines the number of unique memory locations, while data bus width determines the size of data stored at each location. Do not multiply address bits by data bits!