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ITM 151

Digital Logic

TU BITM · Semester 2 · BITM curriculum and programme regulation

Requirement
required
Credits
3
Study Guide
7 units available

Chapter notes

Authoritative study guide across 7 syllabus units

Open a unit to read its study notes.

Unit 1: Introduction· 6 LHs· ~8 marks

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Part 1: Core Concepts (2 Marks)

  • Digital Signal: A discrete, quantized signal represented by finite binary voltage states (Logic 0 / Low: 0V0\text{V}, Logic 1 / High: +5V+5\text{V}), exhibiting superior noise immunity compared to continuous analog waveforms.
  • 2’s Complement Representation: A binary signed-number representation where a negative number is formed by inverting all bits (1’s complement) and adding 1 to the LSB:
    2’s Comp(N)=2n−N\text{2's Comp}(N) = 2^n - N
  • Gray Code (Reflected Binary Code): An unweighted, non-arithmetic cyclic binary code where consecutive numerical values differ by exactly one single bit, eliminating race conditions in optical shaft encoders.
  • Excess-3 Code: An unweighted, self-complementing BCD code obtained by adding 33 (001120011_2) to each decimal digit’s 8421 BCD representation.

Part 2: Structural Frameworks (10 Marks)

Number System Radix Conversion Architecture

  1. DECIMAL (Base 10)
    • / \
    • (Successive Division) (Polynomial Expansion)
    • / \
    • [ BINARY (Base 2) ] <========> [ OCTAL (Base 8) ]
    • \ /
    • (3-Bit Groups) (4-Bit Groups)
    • \ /
  2. HEXADECIMAL (Base 16)

Part 3: Distinction Tables

Basis of Comparison 1’s Complement Subtraction 2’s Complement Subtraction
Mathematical Definition 2n−1−N2^n - 1 - N (Bitwise inversion) 2n−N2^n - N (Bitwise inversion + 1)
Representation of Zero Ambiguous dual zero (+0=0000+0 = 0000, −0=1111-0 = 1111) Unique unambiguous zero (00000000)
End-Around Carry Required; carry bit must be added back to LSB Discarded; end carry is ignored (indicates positive result)
Hardware Arithmetic Complex two-stage addition circuitry Standard single-pass adder hardware used for both +/-

Part 4: Worked Problems & Exam Traps

Worked Subtraction: 2’s Complement Method

Problem: Subtract (25)10(25)_{10} from (14)10(14)_{10} using 8-bit 2’s complement arithmetic:

  1. Binary representations:
    (14)10=000011102(14)_{10} = 00001110_2
    (25)10=000110012(25)_{10} = 00011001_2
  2. Take 2’s complement of subtrahend (2525):
  • 1’s complement of 00011001=1110011000011001 = 11100110
  • Add 1: 11100110+1=11100111211100110 + 1 = 11100111_2
  1. Add (14)+(−25)(14) + (-25):
    00001110+1110011111110101\begin{array}{rc} & 00001110 \\ +& 11100111 \\ \hline & 11110101 \end{array}
  2. Interpretation: No end carry generated   ⟹  \implies Result is negative. Take 2’s complement of result to find magnitude:
  • Invert 11110101  ⟹  0000101011110101 \implies 00001010
  • Add 1: 00001010+1=000010112=(11)1000001010 + 1 = 00001011_2 = (11)_{10}
    ∴Result=−(11)10\therefore \text{Result} = -(11)_{10}

TU Exam Trap: In 2’s complement subtraction, an end carry indicates a positive result (discard the carry); the absence of an end carry indicates a negative result in 2’s complement form.