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ITM 101

Introduction to Computing and Information Technology

TU BITM · Semester 1 · BITM curriculum and programme regulation

Requirement
required
Credits
3
Study Guide
10 units available

Chapter notes

Authoritative study guide across 10 syllabus units

Open a unit to read its study notes.

Unit 1: Computer Fundamentals· 5 LHs· ~6 marks

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Part 1: Core Concepts (2 Marks)

  • Computer System: An electronic, programmable device that accepts raw data as input, processes it systematically In standard academic theory (stored), instructions, produces meaningful information as output, and stores results for future retrieval.
  • Von Neumann Architecture: The foundational theoretical framework of modern computing characterized by a single shared memory structure for both instructions and data, a central processing unit (ALU + Control Unit), and sequential instruction execution.
  • DIKW Hierarchy: The progressive cognitive pipeline transforming unorganized symbols (Data) into contextualized structured facts (Information), actionable understanding (Knowledge), and ethically grounded judgment (Wisdom).
  • Five Computer Generations: 1st (Vacuum Tubes, Machine Language), 2nd (Transistors, Assembly), 3rd (Integrated Circuits, High-Level Languages), 4th (VLSI Microprocessors, Personal Computers), and 5th (ULSI, Parallel Processing, Artificial Intelligence).

Part 2: Structural Frameworks (10 Marks)

Von Neumann Computer Architecture & Internal Subsystems

Von Neumann Computer Architecture Model
Von Neumann Computer Architecture Model
Subsystem / Bus Component Primary Architectural Role Functional Mechanism & Registers Involved
Control Unit (CU) Instruction sequencing & supervisory control Fetches instructions into IR, decodes opcodes, coordinates timing via Program Counter (PC)
Arithmetic Logic Unit (ALU) Arithmetic (+,−,×,÷+,-,\times,\div) and logical (AND,OR,NOT\text{AND}, \text{OR}, \text{NOT}) operations Executes computations using Accumulator (AC) and updates Status/Flag register (Z,S,C,VZ, S, C, V)
Register Array High-speed temporary working memory inside CPU Holds operands, memory pointers (MAR, MBR/MDR), and intermediate results
System Bus: Data Bus Bidirectional operand transfer Moves data between CPU registers and primary memory
System Bus: Address Bus Unidirectional memory addressing Specifies physical memory address for read/write operations (determines maximum RAM address space)
System Bus: Control Bus Unidirectional/Bidirectional control synchronization Transmits READ, WRITE, CLOCK, and INTERRUPT signals across components

Part 3: Distinction Tables

Basis of Comparison Primary Memory (RAM) Secondary Storage (SSD/HDD)
Nature of Volatility Volatile (loses contents when power is disconnected) Non-volatile (preserves state indefinitely without power)
CPU Accessibility Directly addressable by CPU via address/data buses Indirect access via I/O controllers and DMA channels
Access Latency Nanoseconds (5−20 ns5 - 20\text{ ns}) Microseconds to milliseconds (0.05−10 ms0.05 - 10\text{ ms})
Cost per Gigabyte Substantially higher (\text{USD } 3-\text{USD } 5/GB) Economical (\text{USD } 0.02-\text{USD } 0.08/GB)

Part 4: Worked Problems & Exam Traps

Calculation of Bus Bandwidth

Bandwidth (Bytes/sec)=Bus Width (Bytes)×Clock Frequency (Hz)\text{Bandwidth (Bytes/sec)} = \text{Bus Width (Bytes)} \times \text{Clock Frequency (Hz)}

Example: A 64-bit data bus operating at a clock frequency of 3.2 GHz3.2\text{ GHz}:

Width=64 bits8 bits/byte=8 Bytes\text{Width} = \frac{64\text{ bits}}{8\text{ bits/byte}} = 8\text{ Bytes}
Bandwidth=8 Bytes×3.2×109 Hz=25.6×109 Bytes/s=25.6 GB/s\text{Bandwidth} = 8\text{ Bytes} \times 3.2 \times 10^9\text{ Hz} = 25.6 \times 10^9\text{ Bytes/s} = 25.6\text{ GB/s}

TU Exam Trap: Do not confuse the Von Neumann architecture with the Harvard architecture. Von Neumann uses a single unified memory and bus for both instructions and data (causing the ‘Von Neumann Bottleneck’), whereas Harvard utilizes physically separate memories and buses for instructions and data.