Microprocessor and Computer Architecture

Components of a Microprocessor

A microprocessor consists of three primary functional components integrated onto a single semiconductor chip:

1. Arithmetic Logic Unit (ALU): Performs arithmetic operations (addition, subtraction, multiplication) and logical operations (AND, OR, NOT, XOR, comparisons) on binary operands.
2. Register Array (Registers): High-speed internal storage locations used to hold immediate data, memory addresses, intermediate calculation results, instruction codes, and status flags (e.g., Accumulator, Program Counter, Stack Pointer, Instruction Register, General-Purpose Registers).
3. Control and Timing Unit (CU): Generates timing and control signals needed to coordinate and synchronize all internal microprocessor operations and external bus transactions (fetching, decoding, and executing instructions).

DMA Pins in 8085 Microprocessor

Direct Memory Access (DMA) allows high-speed peripheral devices to transfer data directly to/from main memory without continuous CPU intervention. The 8085 microprocessor provides two dedicated hardware pins for DMA operations:

1. HOLD (Pin 39 - Input): An active-high control signal asserted by an external DMA controller (such as Intel 8257/8237) requesting the microprocessor to relinquish control of the address, data, and control buses.
2. HLDA (Hold Acknowledge - Pin 38 - Output): An active-high signal driven by the 8085 microprocessor to acknowledge that it has received the HOLD request and has placed its address, data, and control lines into a high-impedance (tri-state float) condition upon completion of the current machine cycle.

Definition of Operation Code (Opcode)

An Operation Code (Opcode) is the specific binary portion of a machine-language instruction that specifies the exact operation to be performed by the processor (e.g., ADD, SUB, MOV, JMP).

• Structure: In an instruction format, the opcode is accompanied by zero or more operands (or operand addresses).
• Function: During the instruction fetch phase, the opcode is fetched from memory into the Instruction Register (IR) and decoded by the instruction decoder to generate the corresponding micro-operations and control sequences required for execution.

Shift Right vs. Arithmetic Shift Right

Feature	Logical Shift Right (SHR / LSR)	Arithmetic Shift Right (ASR / SAR)
MSB Handling	Always shifts in a 0 into the Most Significant Bit (MSB).	Preserves and duplicates the sign bit (MSB remains unchanged).
Bit Movement	All bits shift one position to the right; LSB enters carry flag.	Bits 0 through $n-2$ shift right; original MSB is copied into bit $n-1$.
Mathematical Meaning	Performs unsigned division by 2.	Performs signed (two’s complement) division by 2, preserving negative sign.
Example (10010110_2)	Result: 01001011_2 (unsigned positive value).	Result: 11001011_2 (remains negative signed value).

Data Transfer Instructions

A Data Transfer Instruction is a category of CPU machine instructions responsible for copying binary data from a source location to a destination location without altering the data contents or modifying CPU condition flags (flags remain unaffected in most architectures like 8085/8086).

Permitted Source/Destination Transfers:

• Register to Register (e.g., MOV B, C)
• Immediate data to Register (e.g., MVI A, 32H)
• Memory to Register (e.g., LDA 2050H or MOV A, M)
• Register to Memory (e.g., STA 3000H or MOV M, B)
• I/O Port to Accumulator (e.g., IN 01H, OUT 02H)

Data Dependency Problem in Pipelining Systems

A Data Dependency Problem (Data Hazard) occurs in an instruction pipeline when an instruction in an early pipeline stage depends on the execution result of a preceding instruction that has not yet completed its write-back stage.

Classification of Data Hazards:

1. RAW (Read After Write - True Dependency): Instruction $J$ tries to read a register/source operand before instruction $I$ writes to it.
2. WAR (Write After Read - Anti-Dependency): Instruction $J$ writes to a destination before instruction $I$ reads its old value.
3. WAW (Write After Write - Output Dependency): Instruction $J$ writes its output before instruction $I$ writes, leading to incorrect final state.

Solutions:

Hardware forwarding (operand bypassing), pipeline stalls (interlocks / bubbles), or compiler instruction scheduling.

Relative Addressing Mode

In Relative Addressing Mode, the effective address (EA) of the operand or target branch instruction is calculated by adding a signed displacement (offset) specified in the instruction to the current contents of the Program Counter (PC):

$$\text{Effective Address (EA)} = \text{Program Counter (PC)} + \text{Displacement}$$

Key Characteristics:

• Position-Independent Code: Enables relocatable code blocks (such as shared libraries or subroutines) because branch targets are calculated relative to the instruction location rather than using absolute physical addresses.
• Short Instruction Size: Allows branching within a localized neighborhood using small 8-bit or 16-bit signed offsets (e.g., short jumps in 8086).

Why We Need an I/O Interface

An Input/Output (I/O) Interface is an essential intermediary electronic subsystem between the CPU/memory and peripheral devices for several critical technical reasons:

1. Speed Mismatch: Microprocessors execute at gigahertz/megahertz speeds, whereas mechanical and human-interface peripherals (keyboards, printers, sensors) operate at orders of magnitude slower speeds. Buffering is required.
2. Signal Level & Format Differences: Peripheral devices often produce analog, serial, or non-TTL voltage levels, whereas the CPU utilizes standardized digital parallel binary signals.
3. Operating Mode Diversity: Peripherals transmit data in serial streams or blocks, requiring parallel-to-serial conversion, parity checking, and error correction.
4. Synchronization & Control: Coordinates data transfers using interrupts, polling, or handshaking signals to avoid data loss.

Limitations of Associative Memory (Content Addressable Memory - CAM)

Associative memory accesses data based on content rather than physical memory address. While offering exceptionally fast search times ($O(1)$ parallel lookup), it suffers from notable limitations:

1. High Hardware Cost & Complexity: Each bit cell in an associative memory array requires dedicated comparison logic (XOR gates) in addition to storage flip-flops, making it much more complex than standard SRAM/DRAM.
2. Higher Power Dissipation: Simultaneous parallel matching across all memory words generates significant heat and consumes substantial electrical power.
3. Limited Storage Capacity: Due to silicon real-estate constraints and gate density, associative memories are restricted to relatively small sizes (used primarily in Translation Lookaside Buffers [TLB] and high-speed cache tag directories).

Micro-operations for POP Operation in a Register Stack

In a computer system utilizing a register stack where the Stack Pointer ($SP$) points to the current top of the stack, the POP micro-operations retrieve the top word into the Data/Destination Register ($DR$) and increment the stack pointer (or decrement in inverted stack implementations):

Micro-operation Sequence:

1. Read Data from Stack Top:
   $$DR \leftarrow M[SP] \quad \text{(or } DR \leftarrow \text{Stack}[SP]\text{)}$$
2. Update Stack Pointer:
   $$SP \leftarrow SP + 1 \quad \text{(in ascending stack) or } SP \leftarrow SP - 1 \quad \text{(in descending stack)}$$
3. Check for Underflow:
   $$\text{If } SP = 0 \text{ (or initial base)}, \text{ set } \text{EMPTY flag} \leftarrow 1$$

Priority Interrupt Systems

A Priority Interrupt System is an arbitration mechanism that establishes a priority hierarchy among multiple concurrent interrupt requests, ensuring that higher-priority devices (e.g., power failure, clock tick, disk controllers) are serviced before lower-priority devices (e.g., keyboard, serial printer).

1. Daisy-Chaining Method (Hardware Serial Polling)

• Architecture: All interrupt-requesting devices are connected in a serial daisy-chain loop. The interrupt request lines are wired-ORed together to the CPU’s INTR pin.
• Operation:
  1. When one or more devices request service, INTR is asserted.
  2. The CPU acknowledges by sending an active-low Interrupt Acknowledge (INTA) signal to the highest-priority device at the head of the chain.
  3. If that device requested the interrupt, it intercepts the signal, places its vector address (VAD) on the data bus, and does not propagate the grant.
  4. If it did not request an interrupt, it passes the grant signal to the next device down the line.
• Advantage: Minimal hardware connections required.
• Disadvantage: Propagation delay increases linearly with the number of devices.

2. Parallel Priority Interrupt (Priority Encoder Method)

• Architecture: Uses dedicated interrupt request lines ($I_0, I_1, \dots, I_{n-1}$) feeding directly into an $8 \times 3$ Priority Encoder circuit (such as the Intel 8259A PIC).
• Operation:
  1. Each device is assigned an input pin where $I_0$ holds highest priority and $I_7$ lowest.
  2. If multiple inputs are simultaneously active, the priority encoder outputs the binary code corresponding to the highest active index.
  3. An Interrupt Status Register (ISR) and Interrupt Mask Register (IMR) allow programmatic masking of individual interrupts.
  4. The generated vector is placed on the bus for immediate vector table dispatching.
• Advantage: Extremely fast arbitration ($O(1)$ gate delay) and dynamic software programmability.

Bus Structure of a Microprocessor System

A Bus is a shared communication pathway consisting of parallel conducting wires that transmit data, addresses, and control signals between the CPU, memory, and peripheral interfaces.

       +--------------------------------------------+
       |             8085 Microprocessor            |
       +-------+---------------+------------+-------+
               |               |            |
  Address Bus  | 16-bit        | Data Bus   | Control Bus
  (Unidirectional)             | 8-bit      | (Bidirectional)
               |               | (Bidir)    |
               v               v            v
       +-------+---------------+------------+-------+
       |             System Main Memory             |
       +--------------------------------------------+
               |               |            |
               v               v            v
       +-------+---------------+------------+-------+
       |          I/O Interfaces & Peripherals      |
       +--------------------------------------------+

1. Address Bus (16-bit Unidirectional in 8085):

• Transmits memory addresses and I/O port addresses from the CPU to memory/peripherals.
• With 16 lines ($A_0 - A_{15}$), the microprocessor can directly address $2^{16} = 65,536$ distinct byte locations ($64\text{ KB}$).
• Unidirectional: signals flow exclusively from the CPU to external components.

2. Data Bus (8-bit Bidirectional in 8085):

• Carries data words and instruction opcodes between the CPU, memory, and I/O modules.
• Bidirectional: the CPU can both read data from memory/inputs and write data to memory/outputs.
• In 8085, the lower 8 address lines ($AD_0 - AD_7$) are time-multiplexed with the 8 data lines to conserve package pins, de-multiplexed using the ALE (Address Latch Enable) signal.

3. Control Bus (Control & Timing Signals):

• Carries command, synchronization, and status signals that coordinate operations across the system.
• Key signals include RD (Read), WR (Write), IO/M (I/O or Memory selection), ALE, RESET, CLK, and interrupt acknowledge.

Addressing Modes in 8085 Microprocessor

The addressing mode defines how the operand of an instruction is specified. 8085 supports five addressing modes; three primary ones are detailed below:

1. Immediate Addressing Mode:

The operand (8-bit or 16-bit data) is specified directly within the instruction itself.

• Characteristics: The data immediately follows the opcode in memory.
• Instruction Format: Opcode + 8-bit/16-bit Data.
• Examples:
  • MVI A, 45H : Move 8-bit immediate value $45_{16}$ into Accumulator $A$.
  • LXI H, 2050H : Load 16-bit immediate address $2050_{16}$ into register pair $HL$.

2. Direct Addressing Mode:

The 16-bit memory address where the operand is stored is specified directly in the instruction bytes following the opcode.

• Characteristics: Requires a 3-byte instruction (1-byte opcode + 2-byte address).
• Examples:
  • LDA 3000H : Load the data byte located at memory address $3000_{16}$ into Accumulator $A$.
  • STA 4000H : Store the contents of Accumulator $A$ into memory address $4000_{16}$.

3. Register Indirect Addressing Mode:

The operand is stored in memory, but its 16-bit memory address is held inside a register pair (most commonly the $HL$ pair, denoted as memory reference $M$).

• Characteristics: The instruction is compact (1 byte) because it only references the register pair holding the pointer.
• Examples:
  • MOV A, M : Move data byte from memory address pointed to by register pair $HL$ into Accumulator $A$.
  • STAX B : Store Accumulator contents into memory address held in register pair $BC$.

Memory Hierarchy and Its Importance

The Memory Hierarchy is a structured architectural organization of computer memory technologies arranged according to access speed, cost per bit, and storage capacity.

                  /\        Speed: Fastest | Cost: Highest | Size: Smallest
                 /  \       -----------------------------------------------
                / CPU\      CPU Registers (<1 ns, ~1 KB)
               /------\
              / Cache  \    L1, L2, L3 SRAM Cache (1-10 ns, MBs)
             /----------\
            / Main Memory\  DRAM / RAM (50-100 ns, GBs)
           /--------------\
          / Secondary Disk \ SSD / NVMe / HDD (microseconds to ms, TBs)
         /------------------\
        / Magnetic Tape / Arc\ Archival Storage (seconds, Petabytes)
        ----------------------

Why Memory Hierarchy is Crucial:

1. Bridging the Processor-Memory Speed Gap: CPUs execute instructions in picoseconds/nanoseconds, while main DRAM access takes 50–100 nanoseconds. Without high-speed cache, the CPU would spend over 90% of its cycles stalled.
2. Economic Viability (Cost Optimization): High-speed static RAM (SRAM) is prohibitively expensive to build in multi-gigabyte capacities. Hierarchical staging delivers near-SRAM speeds at DRAM/disk cost points.
3. Exploiting the Principle of Locality of Reference:
   • Temporal Locality: Items accessed recently are likely to be accessed again soon (loops, subroutines, counters). Kept in cache.
   • Spatial Locality: Items stored at adjacent memory addresses are likely to be accessed consecutively (arrays, sequential instructions). Fetched into cache in multi-word blocks.

4-Bit Binary Incrementer

A 4-bit binary incrementer is a combinational circuit that adds 1 to a 4-bit binary number ($A_3 A_2 A_1 A_0$), generating an output word ($S_3 S_2 S_1 S_0$) and an output carry ($C_4$).

Logic Design Using Half Adders:

An incrementer can be implemented efficiently using four cascaded Half Adders (HAs):

• The least significant bit $A_0$ is added with a constant logic $1$ (input carry $C_0 = 1$).
• Subsequent bits $A_i$ are added to the carry output $C_i$ produced by the preceding stage.

       A0    1 (C0)       A1      C1       A2      C2       A3      C3
        |     |            |       |        |       |        |       |
      +---------+        +-----------+    +-----------+    +-----------+
      | Half    |        | Half      |    | Half      |    | Half      |
      | Adder 0 |        | Adder 1   |    | Adder 2   |    | Adder 3   |
      +----+----+        +----+------+    +----+------+    +----+------+
           |    Carry C1      |   Carry C2     |   Carry C3     |   Carry C4
           |--------+         |-------+        |-------+        |---------> C4
           |                  |                |                |
           v                  v                v                v
          S0                 S1               S2               S3

Boolean Equations:

For each stage $i$ ($0 \le i \le 3$):

• Sum: $S_i = A_i \oplus C_i$
• Carry: $C_{i+1} = A_i \cdot C_i$
• With initial carry input $C_0 = 1$:
  • $S_0 = A_0 \oplus 1 = \overline{A_0}$, and $C_1 = A_0 \cdot 1 = A_0$
  • $S_1 = A_1 \oplus C_1$, and $C_2 = A_1 \cdot C_1$
  • $S_2 = A_2 \oplus C_2$, and $C_3 = A_2 \cdot C_2$
  • $S_3 = A_3 \oplus C_3$, and $C_4 = A_3 \cdot C_3$

Comparison: RISC vs. CISC Architecture

Parameter	RISC (Reduced Instruction Set Computer)	CISC (Complex Instruction Set Computer)
Instruction Set	Small set of simple, fundamental instructions (~50–100).	Large set of diverse, complex instructions (300+).
Instruction Length	Fixed format (typically 32 bits / 4 bytes).	Variable length (e.g., 1 to 15 bytes in x86).
Execution Time	Single-cycle execution for most instructions (pipelined).	Multi-cycle execution per instruction.
Memory Access	Load/Store Architecture: Only LOAD and STORE access memory.	Memory operands can be manipulated directly in ALU instructions.
Addressing Modes	Few, simple addressing modes (register, direct, displacement).	Many complex addressing modes (scaled index, memory indirect).
Registers	Large general-purpose register file (32 or more).	Smaller set of specialized/general registers (8–16).
Control Unit	Hardwired control unit for maximum speed.	Microprogrammed control unit with control ROM.
Pipelining	Highly efficient and straightforward pipeline.	Pipelining is complex due to variable length instructions.
Examples	ARM, MIPS, RISC-V, SPARC.	Intel x86, AMD, Motorola 68000, VAX.

Associative Mapping vs. Direct Mapping in Cache Memory

Cache mapping determines how blocks from main memory are placed into cache slots (cache lines).

1. Direct Mapping:

In direct mapping, each main memory block maps to exactly one specific cache line determined by a fixed modular function:

$$\text{Cache Line} = (\text{Main Memory Block Number}) \pmod{\text{Total Cache Lines}}$$

• Address Split: Divided into [ Tag | Index / Line | Word Offset ].
• Advantages:
  • Extremely simple hardware; lookup requires checking only one cache tag comparator.
  • Very fast access time and inexpensive to build.
• Disadvantages:
  • Conflict Misses (Thrashing): If two frequently used memory blocks map to the identical cache slot, they constantly evict each other even if other cache lines are empty.

2. Fully Associative Mapping:

In fully associative mapping, any block of main memory can reside in any line of the cache.

• Address Split: Divided only into [ Tag | Word Offset ].
• Advantages:
  • Maximum flexibility; virtually eliminates conflict misses. A block is only evicted when the entire cache is full (using replacement algorithms like LRU).
• Disadvantages:
  • Requires parallel search across all tags simultaneously using expensive Content Addressable Memory (CAM) comparators, leading to higher hardware complexity and power consumption.

8085 Assembly Language Program: Addition of Two 8-Bit Numbers

Problem Statement:

Write an assembly program to add two 8-bit binary numbers stored in memory locations 3020H and 3021H. The result (sum) should be stored in memory location 3040H, and if a carry is generated, store the carry in 3041H.

Assembly Source Code:

; ==========================================================
; Program: Addition of two 8-bit binary numbers
; Inputs:  Memory 3020H (First Operand), 3021H (Second Operand)
; Outputs: Memory 3040H (Sum), 3041H (Carry)
; ==========================================================
          ORG 2000H         ; Origin address in RAM

          MVI C, 00H        ; Clear Register C to hold carry (Carry = 0)
          LDA 3020H         ; Load first 8-bit number from 3020H into Accumulator (A)
          MOV B, A          ; Copy first number into Register B
          LDA 3021H         ; Load second 8-bit number from 3021H into Accumulator (A)

          ADD B             ; Add Register B to Accumulator (A = A + B)
          JNC STORE_SUM     ; Jump if No Carry (CY = 0) to STORE_SUM

          INR C             ; If Carry generated (CY = 1), increment Register C

STORE_SUM:
          STA 3040H         ; Store lower 8-bit sum into memory location 3040H
          MOV A, C          ; Move carry flag value from Register C to Accumulator
          STA 3041H         ; Store carry (00H or 01H) into memory location 3041H

          HLT               ; Halt the microprocessor execution

Step-by-Step Program Walkthrough:

1. MVI C, 00H: Initializes carry counter register $C$ to 00H.
2. LDA 3020H: Fetches the first operand from memory address 3020H into accumulator $A$.
3. MOV B, A: Saves the first operand into register $B$ so accumulator can receive the second operand.
4. LDA 3021H: Fetches second operand from 3021H into $A$.
5. ADD B: The ALU adds $B$ to $A$. Flags (Carry CY, Zero Z, Sign S) are updated based on sum.
6. JNC STORE_SUM: Evaluates Carry flag. If no carry was produced, execution jumps over INR C.
7. INR C: Executes only if carry occurred, setting $C = \text{01H}$.
8. STA 3040H: Writes sum to 3040H.
9. STA 3041H: Writes carry byte to 3041H.

Arithmetic Pipeline for Floating-Point Addition

Floating-point numbers are represented in normalized scientific notation:

$$X = M_x \times 2^{E_x}, \quad Y = M_y \times 2^{E_y}$$

where $M$ denotes the fractional mantissa and $E$ represents the exponent.

Adding two floating-point binary numbers requires an arithmetic pipeline organized into four discrete sub-operation stages:

 [ Input Operands: X = Mx * 2^Ex, Y = My * 2^Ey ]
                        |
                        v
        +-------------------------------+
        | Stage 1: Compare Exponents    | ---> Determine larger exponent
        |          and Difference (d)   |      d = |Ex - Ey|
        +---------------+---------------+
                        |
                        v
        +-------------------------------+
        | Stage 2: Align the Mantissas  | ---> Shift mantissa of smaller
        |          (Right-shift smaller)|      number right by d positions
        +---------------+---------------+
                        |
                        v
        +-------------------------------+
        | Stage 3: Add / Subtract       | ---> Add aligned mantissas:
        |          Mantissas            |      Mz = Mx' + My'
        +---------------+---------------+
                        |
                        v
        +-------------------------------+
        | Stage 4: Normalize Result &   | ---> Shift Mz left/right until
        |          Adjust Exponent      |      MSB is 1; update Ez
        +---------------+---------------+
                        |
                        v
          [ Final Output: Z = Mz * 2^Ez ]

Detailed Stage Breakdown:

1. Stage 1 — Compare Exponents by Subtraction:

   • The exponents $E_x$ and $E_y$ are subtracted: $d = E_x - E_y$.
   • The larger exponent is chosen as the tentative exponent of the result ($E_z = \max(E_x, E_y)$).
   • If $E_x = E_y$, alignment is bypassed ($d = 0$).

2. Stage 2 — Align Mantissas (Shifter):

   • The mantissa belonging to the operand with the smaller exponent is shifted to the right by $d$ bit positions.
   • This equalizes the power bases of both operands so fractional parts can be directly added.

3. Stage 3 — Add Mantissas:

   • The two mantissas (one unshifted and one right-shifted) are added using a high-speed parallel binary adder.
   • Result: intermediate mantissa $M_z$.

4. Stage 4 — Normalize the Result:

   • If mantissa addition overflowed (carry out of MSB = 1), $M_z$ is shifted right by one bit and exponent $E_z$ is incremented by 1.
   • If mantissa has leading zeros, $M_z$ is shifted left until the leading non-zero bit is in the normalized fraction position, and $E_z$ is decremented accordingly.

Strobe Control Method for Asynchronous Data Transfer

In Asynchronous Data Transfer, the transmitting and receiving units operate on separate, independent internal clock frequencies. Data transfer must be coordinated using control signals rather than a shared clock.

The Strobe Control Method employs a single control signal (the “strobe”) to indicate the initiation or readiness of a transfer.

---

1. Source-Initiated Strobe Transfer

In this method, the transmitting (source) unit initiates and drives the data transfer.

Source Unit                              Destination Unit
   +---------+        Data Bus [8-bit]       +-------------+
   |         | ============================> |             |
   |         |         Strobe Pulse          |             |
   |         | ----------------------------> |             |
   +---------+                               +-------------+

Timing Diagram:
Data Bus:    ----------< Valid Data Word >--------------
                                 +-------+
Strobe:      --------------------+       +--------------

Step-by-Step Sequence:

1. The source unit places valid data onto the data bus.
2. After a brief propagation delay (ensuring data lines stabilize), the source activates the Strobe line (logic high pulse).
3. The destination unit senses the active strobe pulse and latches the data from the data bus into its input buffer register.
4. The source deactivates the strobe and removes data from the bus.

---

2. Destination-Initiated Strobe Transfer

In this method, the receiving (destination) unit initiates the request for data from the source unit.

Source Unit                              Destination Unit
   +---------+        Data Bus [8-bit]       +-------------+
   |         | ============================> |             |
   |         |         Strobe Pulse          |             |
   |         | <---------------------------- |             |
   +---------+                               +-------------+

Timing Diagram:
                                 +-------+
Strobe:      --------------------+       +--------------
Data Bus:    ----------------------< Valid Data Word >--

Step-by-Step Sequence:

1. The destination unit activates the Strobe signal requesting the source to send data.
2. The source unit detects the strobe pulse, retrieves data, and places it onto the data bus.
3. The destination unit latches the data off the bus and removes the strobe pulse.

---

Critical Limitation of Strobe Control (Why Handshaking is Preferred):

• Lack of Acknowledgment: The source has no way of verifying whether the destination actually received the data before placing new data on the bus.
• If the destination is slow or busy, data will be lost (overrun). Handshaking solves this by using two reciprocal lines (Data Ready and Data Accepted).

Internal Architecture of 8085 Microprocessor

The Intel 8085 is an 8-bit NMOS microprocessor packaged in a 40-pin DIP IC operating on a single $+5\text{V}$ power supply with an internal clock frequency of $3.072\text{ MHz}$.

                 +-----------------------------------------------+
                 |        8085 FUNCTIONAL ARCHITECTURE           |
                 +-----------------------------------------------+
                 |  [ Interrupt Control ]     [ Serial I/O ]     |
                 |  TRAP, RST7.5-5.5, INTR    SID, SOD           |
                 +-----------------------+-----------------------+
                                         |
                               8-bit Internal Bus
       +-----------------------+-------------------------+
       |                       |                         |
       v                       v                         v
+-------------+         +-------------+           +--------------+
| Accumulator |         | Temp Reg (W)|           | Instruction  |
|    (8-bit)  |         +-------------+           | Register(IR) |
+------+------+         | Temp Reg (Z)|           +-------+------+
       |                +------+------+                   |
       v                       |                          v
+-------------+                |                  +--------------+
|   ALU       |<---------------+                  | Instruction  |
|  (8-bit)    |                                   |   Decoder    |
+------+------+                                   +-------+------+
       |                                                  |
       +---------> [ Flag Register (5 Flags) ]            v
                                                  +--------------+
       +------------------------------------+     | Timing &     |
       |       General Purpose Registers    |     | Control Unit |
       |     B (8)   |   C (8)              |     +--------------+
       |     D (8)   |   E (8)              |
       |     H (8)   |   L (8)              |
       |     Stack Pointer (SP - 16 bit)    |
       |     Program Counter (PC - 16 bit)  |
       |     Incrementer / Decrementer      |
       +------------------+-----------------+
                          |
             +------------+------------+
             |                         |
             v                         v
    [ Address Buffer ]       [ Address / Data Buffer ]
     A15 - A8 (8-bit)           AD7 - AD0 (8-bit)

Major Functional Units:

1. Arithmetic and Logic Unit (ALU):

   • Performs 8-bit arithmetic operations (addition, subtraction) and logical operations (AND, OR, XOR, complement).
   • Operates on operands from the Accumulator and temporary registers ($W$ and $Z$).

2. Accumulator and Status Flags (Flag Register):

   • Accumulator (A): Primary 8-bit register that holds one operand and receives ALU results.
   • Flag Register (F): 5 flip-flops reflecting ALU status:
     • $S$ (Sign): Set if MSB ($D_7$) of result is 1 (negative).
     • $Z$ (Zero): Set if result is exactly 0.
     • $AC$ (Auxiliary Carry): Set if carry generated from bit $D_3$ to $D_4$ (used for BCD).
     • $P$ (Parity): Set if result contains even number of 1s.
     • $CY$ (Carry): Set if arithmetic operation produced carry out of MSB $D_7$.

3. Register Array:

   • General Purpose Registers ($B, C, D, E, H, L$): Can be used individually as 8-bit registers or paired as 16-bit register pairs ($BC, DE, HL$) for 16-bit pointers.
   • Program Counter (PC - 16 bits): Holds memory address of next instruction to be fetched; auto-increments after fetch.
   • Stack Pointer (SP - 16 bits): Holds memory address of the current top of the stack in RAM.

4. Instruction Register and Decoder:

   • Fetches 8-bit opcode into IR and decodes it to determine micro-operation timing signals.

5. Timing and Control Unit:

   • Generates signals: CLK OUT, ALE, RD, WR, IO/M, S0, S1, RESET IN/OUT.

6. Interrupt Control & Serial I/O:

   • Hardware interrupts: TRAP (highest, non-maskable), RST 7.5, RST 6.5, RST 5.5, INTR.
   • Serial lines: SID (Serial Input Data) and SOD (Serial Output Data).

Divide Overflow and Binary Division Algorithm

1. Divide Overflow:

A Divide Overflow occurs in fixed-point binary division when the magnitude of the quotient is too large to be represented within the allocated quotient register.

• In computer hardware dividing a $2n$-bit dividend by an $n$-bit divisor, the quotient register is typically $n$ bits wide.
• Overflow Condition: If the higher-order $n$ bits of the dividend ($A$) are greater than or equal to the divisor ($B$):
  $$\text{If } |A| \ge |B|, \quad \text{Divide Overflow occurs!}$$
  When detected, the hardware sets a Divide-Overflow flip-flop and aborts the division to prevent invalid arithmetic results.

---

2. Division: $+(16)_{10}$ by $-(3)_{10}$

Operand Setup:

• Dividend: $+(16)_{10} = 00010000_2$ (Magnitude = $16$)
• Divisor: $-(3)_{10}$, absolute magnitude = $(3)_{10} = 00011_2$
• Since signs are opposite ($+$ and $-$):
  $$\text{Sign of Quotient} = (+) \oplus (-) = (-)$$
  $$\text{Sign of Remainder} = \text{Same as Dividend} = (+)$$

Using the standard Restoring Division Algorithm on positive magnitudes ($16 \div 3$):

• Dividend in $Q = 10000_2$ (5 bits), Register $A = 00000_2$, Divisor $B = 00011_2$, Counter $n = 5$.

Step-by-Step Execution Table:

Step / Action	Register A	Register Q	Counter ($n$)	Description
Initial	00000	10000	5	Load magnitudes of A and Q
Cycle 1: Shift Left	00001	0000_		Left shift $[A, Q]$
$A \leftarrow A - B$	11110	0000_		$A < 0$ (Negative result)
Restore $A$, $Q_0 \leftarrow 0$	00001	00000	4	Restore $A \leftarrow A + B$, set $Q_0 = 0$
Cycle 2: Shift Left	00010	0000_		Left shift $[A, Q]$
$A \leftarrow A - B$	11111	0000_		$A < 0$ (Negative)
Restore $A$, $Q_0 \leftarrow 0$	00010	00000	3	Restore $A$, set $Q_0 = 0$
Cycle 3: Shift Left	00100	0000_		Left shift $[A, Q]$
$A \leftarrow A - B$	00001	0000_		$00100 - 00011 = 00001$ ($\ge 0$, Positive!)
Set $Q_0 \leftarrow 1$	00001	00001	2	Successful subtraction, $Q_0 = 1$
Cycle 4: Shift Left	00010	0001_		Left shift $[A, Q]$
$A \leftarrow A - B$	11111	0001_		$A < 0$ (Negative)
Restore $A$, $Q_0 \leftarrow 0$	00010	00010	1	Restore $A$, set $Q_0 = 0$
Cycle 5: Shift Left	00100	0010_		Left shift $[A, Q]$
$A \leftarrow A - B$	00001	0010_		$00100 - 00011 = 00001$ ($\ge 0$, Positive!)
Set $Q_0 \leftarrow 1$	00001	00101	0	$Q_0 = 1$, Counter reached 0 (Finish)

Final Result:

• Quotient ($Q$): $00101_2 = (5)_{10}$. With negative sign: Quotient $= -5$
• Remainder ($A$): $00001_2 = (1)_{10}$. With positive sign: Remainder $= +1$
• Verification: $(16)_{10} = (-3)_{10} \times (-5)_{10} + (+1)_{10} = 15 + 1 = 16$ (Accurate).