Microprocessor and Computer Architecture

Pass path: Define microprocessor, state the three system buses (Address, Data, Control), and explain the SAP-1 architecture. Top path: Differentiate bus width vs memory addressability, analyze tri-state buffer operation, and trace the SAP-1 fetch-execute instruction cycle.

Part 1: Core Concepts (2 Marks)

• ★ Microprocessor: A programmable, multipurpose, clock-driven, semiconductor integrated circuit (IC) that fetches binary instructions from memory, decodes them, and executes arithmetic and logic operations.
• ★ System Buses:
  • Address Bus: Unidirectional bus carrying physical memory addresses from CPU to memory/IO; width determines maximum addressable memory ($2^k$).
  • Data Bus: Bidirectional bus transferring actual data and instructions between CPU, memory, and peripheral controllers.
  • Control Bus: Collection of unidirectional and bidirectional lines transmitting timing, read/write, and status control strobes.
• ★ Tri-State Buffer: A logic circuit with three operational states: Logic High (1), Logic Low (0), and High-Impedance ($Z$, float/disconnected). Allows multiple devices to share common system buses without bus contention.

Part 2: Structural Frameworks (10 Marks)

1. Architecture and Operation of Simple-As-Possible (SAP-1) Computer

When asked to evaluate the fundamental architectural blocks of SAP-1:

1. Program Counter (PC): 4-bit register that generates memory addresses of instructions to fetch; counts sequentially from 0000 to 1111.
2. Memory Address Register (MAR): Latches 4-bit address from system bus during fetch state.
3. RAM (16 x 8): 16 bytes of memory storing instructions (upper nibble opcode, lower nibble operand) and data.
4. Instruction Register (IR): 8-bit register holding fetched instruction; splits opcode to Controller-Sequencer and operand to bus.
5. Controller-Sequencer: Generates micro-timing control words ($CON$) during T-states ($T_1$ to $T_6$) to coordinate register transfers.
6. Accumulator & B-Register: 8-bit registers buffering inputs to the Adder-Subtractor.
7. Instruction Cycle Mechanics:
   • $T_1$: Address state ($PC \rightarrow MAR$).
   • $T_2$: Increment state ($PC = PC + 1$).
   • $T_3$: Memory state ($RAM \rightarrow IR$).
   • $T_4 - T_6$: Execution states (e.g., $LDA, ADD, SUB, OUT, HLT$).

Part 3: Distinction Tables

SAP-1 vs. SAP-2 Architecture Comparison

Part 4: Worked Problems & Exam Traps

Problem 1 (Standard): Memory Address Space Calculation

A microprocessor has a 16-bit address bus and an 8-bit data bus. Calculate the maximum physical memory capacity in bytes and kilobytes.

• Calculation:

  Swipe to see the full formula↔

  $$\text{Total Addressable Locations} = 2^{16} = 65{,}536 \text{ memory words}$$
  Since the data bus is 8-bit (1 byte per word):

  Swipe to see the full formula↔

  $$\text{Total Capacity} = 65{,}536 \times 1 \text{ byte} = 65{,}536 \text{ Bytes}$$

  Swipe to see the full formula↔

  $$\text{Capacity in KB} = \frac{65{,}536}{1024} = 64 \text{ KB}$$

Students lose marks here because they state that the address bus is bidirectional. The address bus is strictly unidirectional (CPU drives addresses outward to memory and peripherals).