Microprocessor and Computer Architecture

Answer:

Answer:

• Addressing Mode: The rule or technique by which the CPU interprets an instruction’s operand field to locate the effective memory address of the required data.
• Immediate Addressing: The actual operand data is specified directly within the instruction itself. 8085 Example: MVI A, 45H (Loads immediate hex byte 45H directly into Accumulator).
• Register Indirect Addressing: The instruction specifies a register pair that holds the physical memory address where the operand is stored. 8085 Example: MOV A, M (Loads Accumulator with data from memory address pointed by the HL register pair).

Answer:

• Program Counter (PC): A 16-bit internal register that holds the memory address of the next instruction to be fetched and executed. It is automatically incremented as instructions are fetched sequentially, or updated during branch/jump instructions.
• Stack Pointer (SP): A 16-bit register that stores the memory address of the current top of the LIFO (Last-In, First-Out) stack structure in RAM. It decrements when data is pushed (PUSH or subroutine CALL) and increments when data is popped (POP or RET).

Answer:

• Cache Hit: Occurs when the memory word or block requested by the CPU is already present in cache memory, allowing immediate retrieval at high speed ($t_{\text{hit}}$).
• Cache Miss: Occurs when the requested memory word is absent from cache, requiring an access to slower main RAM (imposing a miss penalty).
• Hit Ratio ($H$): The fraction of total memory references satisfied by the cache:
  $$H = \frac{\text{Number of Cache Hits}}{\text{Total Memory References} \; (\text{Hits} + \text{Misses})}$$
  Miss ratio is $M = 1 - H$.

Answer:

• Interrupt: An asynchronous hardware or software signal that suspends the CPU’s normal program execution sequence, saves context, and forces execution of an Interrupt Service Routine (ISR).
• Maskable Interrupt: An interrupt whose servicing can be enabled or disabled/ignored by software commands (e.g. EI / DI instructions in 8085; e.g., RST 7.5, RST 6.5, INTR). Used for normal peripheral I/O.
• Non-Maskable Interrupt (NMI): An interrupt that the CPU cannot ignore or mask under any software condition (e.g., TRAP in 8085). Reserved for catastrophic events like power failure or hardware memory parity faults.

8085 Microprocessor Architecture and Maximum Number Assembly Program

a) 8085 Functional Internal Architecture

1. Functional Units

1. Arithmetic and Logic Unit (ALU): Performs 8-bit arithmetic (add, subtract) and logical (AND, OR, XOR, compare) operations.
2. Accumulator (Register A): 8-bit register serving as the primary source operand and destination for all ALU results.
3. General Purpose Registers: Six 8-bit registers ($B, C, D, E, H, L$) that can function individually or as 16-bit register pairs ($BC, DE, HL$) where $HL$ serves as the default memory pointer $M$.
4. Flags Register (F): 5 flip-flops recording arithmetic status:
   • S (Sign): Set if MSB ($D_7$) is 1 (negative).
   • Z (Zero): Set if ALU result is exactly zero.
   • AC (Auxiliary Carry): Set on carry from bit $D_3$ to $D_4$ (for BCD).
   • P (Parity): Set if result contains even number of 1s.
   • CY (Carry): Set on arithmetic overflow/carry beyond bit $D_7$.
5. Timing and Control Unit: Decodes instructions and generates synchronization pulses (ALE, RD, WR, IO/M).

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b) 8085 Assembly Language Program: Find Maximum Value

; Problem: Find maximum byte in array of length N
; Array length N stored at: 2050H
; Array data starts at:    2051H
; Store maximum result at: 3050H

          LXI H, 2050H    ; HL points to array count N
          MOV C, M        ; Load counter C with array size N
          INX H           ; HL points to first array element (2051H)
          MOV A, M        ; Initialize Accumulator with first element
          DCR C           ; Decrement counter (1 element already processed)
          JZ STORE        ; If array had only 1 element, jump to store

LOOP:     INX H           ; HL points to next element
          CMP M           ; Compare Accumulator with memory element M
                          ; If A >= M: Carry flag CY = 0
                          ; If A < M:  Carry flag CY = 1
          JNC SKIP        ; If A >= M, do not replace, skip
          MOV A, M        ; If A < M, load new maximum into Accumulator

SKIP:     DCR C           ; Decrement remaining elements counter
          JNZ LOOP        ; Repeat until all elements examined

STORE:    STA 3050H       ; Store maximum value in memory address 3050H
          HLT             ; Terminate program execution

Step-by-Step Register Trace

• Let array at 2050H contain: Count $N = 3$, elements: [25H, 64H, 12H].

Instruction Pipelining, Hazard Analysis, and Speedup Calculation

a) 5-Stage Classic RISC Instruction Pipeline

1. IF (Instruction Fetch): The instruction pointed to by the PC is fetched from memory/I-Cache into the Instruction Register (IR); PC is incremented.
2. ID (Instruction Decode / Register Fetch): The instruction opcode is decoded in the control logic; source operands are read from the register file.
3. EX (Execute / ALU): ALU performs the arithmetic operation, computes memory effective address for loads/stores, or evaluates branch conditions.
4. MEM (Memory Access): Data memory or D-Cache is accessed to read (load) or write (store) data operands.
5. WB (Write Back): The resulting data from ALU or memory is written back to the destination register in the register file.

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b) Pipeline Hazards and Mitigation Techniques

1. Structural Hazards

• Cause: Hardware resource conflict when two pipeline stages attempt to access the exact same physical hardware component in the same clock cycle. Example: IF stage fetching instruction from RAM while MEM stage is simultaneously reading data from RAM.
• Remedy: Separate instruction and data caches (Harvard memory split) or duplicating hardware execution units.

2. Data Hazards

Occur when an instruction depends on the result of a previous instruction that is still in flight in the pipeline:

• RAW (Read After Write - True Dependency): Instruction $j$ tries to read a register before instruction $i$ writes to it. Remedy: Operand Forwarding (Bypassing) routes ALU output directly from EX/MEM stage registers to the EX stage of the next instruction without waiting for WB; or inserting software/hardware pipeline stalls (bubbles).
• WAR (Write After Read - Anti-dependency): Occurs in out-of-order execution when $j$ tries to write before $i$ reads.
• WAW (Write After Write - Output dependency): Occurs when $j$ overwrites a register before an earlier instruction $i$ writes. Remedy for WAR/WAW: Register Renaming.

3. Control Hazards (Branch Hazards)

• Cause: Conditional branches change the PC, but the branch outcome and target address are not resolved until the EX/MEM stage, during which incorrect sequential instructions have already been fetched.
• Remedy: Branch Prediction (Dynamic 2-bit saturating branch history tables), Delayed Branching with branch delay slots.

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c) Pipeline Speedup Calculation

• Number of stages $k = 5$
• Number of instructions $n = 1000$
• Pipelined clock cycle $\tau_k = 2\text{ ns}$
• Unpipelined execution time per instruction $\tau_u = 10\text{ ns}$

1. Total Unpipelined Time ($T_u$)

$$T_u = n \times \tau_u = 1000 \times 10\text{ ns} = 10,000\text{ ns}$$

2. Total Pipelined Time ($T_k$)

The first instruction takes $k$ cycles to fill the pipe; the remaining $(n - 1)$ instructions complete at the rate of 1 instruction per cycle:

$$T_k = (k + n - 1) \times \tau_k = (5 + 1000 - 1) \times 2\text{ ns} = 1004 \times 2\text{ ns} = 2,008\text{ ns}$$

3. Speedup ($S$)

$$S = \frac{T_u}{T_k} = \frac{10,000\text{ ns}}{2,008\text{ ns}} \approx \mathbf{4.98}$$

The 5-stage pipeline achieves a near-ideal $4.98\times$ speedup.

Cache Mapping Techniques and Set-Associative Address Partitioning

a) Comparison of Cache Mapping Techniques

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b) Mathematical Address Bit Allocation Calculation

1. System Parameters

• Total Address Space: 32 bits ($2^{32}$ bytes = 4 GB byte-addressable memory)
• Cache Size = $64\text{ KB} = 64 \times 1024\text{ bytes} = 65,536\text{ bytes} = 2^{16}\text{ bytes}$
• Block Size (Line Size) = $64\text{ bytes} = 2^6\text{ bytes}$
• Set Associativity ($k$) = 4-way ($k = 4 = 2^2$ lines per set)

2. Block (Word) Offset Calculation

The block offset determines the exact byte within a 64-byte cache block:

$$\text{Block Offset Bits} = \log_2(\text{Block Size}) = \log_2(64) = \log_2(2^6) = \mathbf{6\text{ bits}}$$

3. Set Index Calculation

Total number of lines in cache:

$$\text{Total Lines} = \frac{\text{Cache Size}}{\text{Block Size}} = \frac{65,536\text{ bytes}}{64\text{ bytes}} = 1024\text{ lines} = 2^{10}$$

Total number of sets in a 4-way set-associative cache:

$$\text{Number of Sets} = \frac{\text{Total Lines}}{k} = \frac{1024}{4} = 256\text{ sets} = 2^8$$

$$\text{Set Index Bits} = \log_2(\text{Number of Sets}) = \log_2(256) = \log_2(2^8) = \mathbf{8\text{ bits}}$$

4. Tag Bits Calculation

The remaining most significant bits constitute the Tag:

$$\text{Tag Bits} = \text{Total Address Bits} - (\text{Set Index Bits} + \text{Block Offset Bits})$$

$$\text{Tag Bits} = 32 - (8 + 6) = 32 - 14 = \mathbf{18\text{ bits}}$$

5. 32-Bit Memory Address Partitioning Map

Total check: $18 + 8 + 6 = 32$ bits.

I/O Organization and Direct Memory Access (DMA) Mechanics

a) Comparison of I/O Transfer Techniques

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b) DMA Controller Architecture and Bus Handshake

1. Core Internal Registers of DMA Controller (Intel 8237)

• Memory Address Register: Stores the starting RAM memory address for data read/write. Increments after each byte transferred.
• Byte Count Register: Stores the number of bytes to transfer. Decrements after each byte until reaching zero (Terminal Count - TC).
• Control / Status Register: Configures transfer direction (Memory-to-I/O or I/O-to-Memory) and DMA channel priority.

2. Bus Handshake Protocol (HOLD and HLDA)

1. When a high-speed peripheral (e.g., Disk Controller) needs to transfer a block, it asserts DMA Request (DREQ).
2. The DMA Controller asserts the HOLD line to the CPU, requesting complete ownership of the system address, data, and control buses.
3. The CPU completes its current bus machine cycle, floats its buses into a high-impedance state, and replies with Hold Acknowledge (HLDA).
4. The DMA controller asserts DACK to the peripheral and drives memory address and read/write control lines directly, transferring data directly between peripheral and RAM without passing through CPU registers.
5. Upon transferring the final byte, the DMA Controller drops HOLD, and the CPU resumes normal bus control.

3. Data Transfer Modes

• Burst Mode (Block Transfer): The DMA controller retains continuous control of system buses until the entire block of data is completely transferred. Delivers maximum transfer speed, but locks the CPU out of main memory for prolonged intervals.
• Cycle Stealing Mode: The DMA controller acquires the bus, transfers exactly one byte/word, and immediately relinquishes the bus back to the CPU. It “steals” idle CPU memory cycles, allowing CPU execution and high-speed I/O to interleave seamlessly without starving the processor.

Computer Architecture Solution: Smart Electric Grid Telemetry Node

a) Core Processor Architecture: Embedded RISC vs. CISC Selection

1. Architectural Selection: 32-Bit RISC (ARM Cortex-M / RISC-V RV32IMF)

• Deterministic Instruction Timing: RISC architectures feature fixed-length 32-bit instructions executing in uniform, single-cycle or predictable pipelined stages. In power grid safety systems, deterministic execution is critical for real-time fault guarantees; CISC variable-length instructions (1 to 15 bytes in x86) cause unpredictable instruction decoding jitter.
• Register File Sizing (32 General-Purpose 32-bit Registers): A large orthogonal register file ($R_0 - R_{31}$) minimizes memory spills. Time-critical sensor variables, Fast Fourier Transform (FFT) coefficients, and threshold limits are pinned permanently inside CPU registers.
• Hardware DSP / Single-Cycle MAC (Multiply-Accumulate): Real-time RMS voltage calculation requires continuous quadratic summation ($\sum V_i^2$). A hardware single-cycle MAC unit computes $A \leftarrow A + (X \times Y)$ in $5\text{ ns}$, processing sensor streams without CPU stalls.

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b) Memory Hierarchy Optimization and AMAT Calculation

1. Average Memory Access Time (AMAT) Formulation

For a two-level cache hierarchy, AMAT is:

$$\text{AMAT} = t_{L1} + (1 - H_1) \times \left( t_{L2} + (1 - H_2) \times t_{\text{RAM}} \right)$$

where:

• $t_{L1} = 5\text{ ns}$ (1 clock cycle)
• $H_1 = 0.95 \implies \text{Miss Rate } M_1 = 1 - 0.95 = 0.05$
• $t_{L2} = 20\text{ ns}$ (4 clock cycles)
• $H_2 = 0.90 \implies \text{Local Miss Rate } M_2 = 1 - 0.90 = 0.10$
• $t_{\text{RAM}} = 60\text{ ns}$ (12 clock cycles)

2. Step-by-Step AMAT Calculation

1. L2 Miss Penalty to DRAM:
   $$\text{Penalty}_{L2} = t_{L2} + (1 - H_2) \times t_{\text{RAM}} = 20\text{ ns} + (0.10 \times 60\text{ ns}) = 20\text{ ns} + 6\text{ ns} = \mathbf{26\text{ ns}}$$
2. Overall AMAT:
   $$\text{AMAT} = t_{L1} + (1 - H_1) \times \text{Penalty}_{L2}$$
   $$\text{AMAT} = 5\text{ ns} + (0.05 \times 26\text{ ns}) = 5\text{ ns} + 1.3\text{ ns} = \mathbf{6.30\text{ ns}}$$

• Conclusion: Cache hierarchy reduces effective memory access latency from $60\text{ ns}$ down to $6.30\text{ ns}$—a $9.52\times$ memory access speedup!

3. Cache Write Policy: Write-Back with Dirty Bit

• Write-Through: Every write must update both cache and main DRAM. At 3.2 MB/s continuous ADC input, Write-Through saturates the 60ns DRAM bus, creating severe bus contention stalls.
• Write-Back (Selected): Writes update only the high-speed L1/L2 cache blocks. A Dirty Bit flags modified lines; data is written back to DRAM only when a cache line is evicted. This isolates the CPU and DMA from slow DRAM latency during steady-state monitoring.

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c) DMA Subsystem and Sub-500ns Interrupt Architecture

1. Circular Ping-Pong (Dual Buffer) DMA Configuration

[16-Channel ADC]
       |
       v (Hardware DREQ trigger)
[DMA Controller Channel 0]
       |
       +---> [Buffer A (RAM)] ---> Processed by CPU (FFT & Surge Algorithm)
       |
       +---> [Buffer B (RAM)] ---> Concurrently filled by DMA (Zero CPU overhead)

• Ping-Pong Buffer Mechanism: While the DMA engine autonomously writes incoming ADC samples into Buffer A, the CPU processes completed waveform samples in Buffer B.
• When Buffer A fills, DMA controller asserts a half-transfer interrupt and automatically flips write pointers to Buffer B. Zero CPU cycles are wasted copying sensor bytes.

2. Nested Vectored Interrupt Controller (NVIC) for Sub-500ns Response

To guarantee breaker trip under $500\text{ ns}$:

1. Zero-Latency Hardware Vectoring: The hardware surge comparator output is wired directly to Interrupt Line 0 (highest priority NMI). The NVIC hardware fetches the ISR address directly from the vector table in hardware without software polling.
2. Hardware Register Stacking: In ARM Cortex-M, the processor hardware automatically pushes caller registers ($R_0-R_3, R_{12}, LR, PC, xPSR$) onto the stack in 12 clock cycles ($12 \times 5\text{ ns} = 60\text{ ns}$).
3. Dedicated Trip Breaker ISR Execution:
   • At $t = 60\text{ ns}$, CPU enters ISR.
   • Executes single-cycle atomic GPIO set instruction: *GPIO_BSRR = (1 << TRIP_PIN); ($5\text{ ns}$).
   • Total latency from physical fault detection to breaker trip pulse is $< 100\text{ ns}$, well within the stringent $500\text{ ns}$ safety requirement.